`timescale 1ps/1ps
module regfile(
    input           clk
,   input           rst_n
,   input           write
,   input  [3:0]    addr
,   input  [127:0]  din
,   output [127:0]  dout
);

reg [127:0] mem [0:10];

always @(posedge clk) begin
    if(!rst_n)begin
        mem[0] <= 'd0;
        mem[1] <= 'd0;
        mem[2] <= 'd0;
        mem[3] <= 'd0;
        mem[4] <= 'd0;
        mem[5] <= 'd0;
        mem[6] <= 'd0;
        mem[7] <= 'd0;
        mem[8] <= 'd0;
        mem[9] <= 'd0;
        mem[10]<= 'd0;
    end else if(write)
        mem[addr] <= din;
end    


assign dout = mem[addr];

endmodule